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  1. /*
  2.     File:        G4Monitor.h
  3.  
  4.     Contains:    xxx put contents here xxx
  5.  
  6.     Version:    xxx put version here xxx
  7.  
  8.     Copyright:    © 1998_1999 by Apple Computer, Inc., all rights reserved.
  9.  
  10.     File Ownership:
  11.  
  12.         DRI:                xxx put dri here xxx
  13.  
  14.         Other Contact:        xxx put other contact here xxx
  15.  
  16.         Technology:            xxx put technology here xxx
  17.  
  18.     Writers:
  19.  
  20.         (DC)    Doug Clarke
  21.  
  22.     Change History (most recent first):
  23.  
  24.         <1*>      2/1/99    DC        testing
  25.        <CS1>    11/25/98    DC        first checked in
  26. */
  27.  
  28. //PerformanceMonitor604.h
  29.  
  30. #ifndef __PerformanceMonitor604__
  31. #define __PerformanceMonitor604__
  32.  
  33. //#include "InstrumentationMacros.h"
  34.  
  35. #ifdef __cplusplus
  36. extern "C" {
  37. #endif
  38.  
  39.  
  40. // Constants for MMCR0 register
  41. enum
  42. {
  43.     kMMCR0_PMC1_nothing                     = 0 <<6,
  44.     kMMCR0_PMC1_processor_cycles             = 1 <<6,
  45.     kMMCR0_PMC1_instructions_completed         = 2 <<6,
  46.     kMMCR0_PMC1_time_base_bit_transitions    = 3 <<6,
  47.     kMMCR0_PMC1_instructions_dispatched        = 4 <<6,
  48.     kMMCR0_PMC1_eieio_Instructions            = 5 <<6,
  49.     kMMCR0_PMC1_ITLB_tablewalk_cycles        = 6 <<6,
  50.     kMMCR0_PMC1_vperm_instructions            = 7 <<6,
  51.     kMMCR0_PMC1_vsfx_wait                    = 8 <<6,
  52.     kMMCR0_PMC1_instruction_address_match    = 9 <<6,
  53.     kMMCR0_PMC1_data_address_match            = 10<<6,
  54.     kMMCR0_PMC1_load_miss_latency_over_TH    = 11<<6,
  55.     kMMCR0_PMC1_unresolved_branches            = 12<<6,
  56.     kMMCR0_PMC1_dispatch_stall_bad_branch    = 13<<6,
  57.     kMMCR0_PMC1_mfvscr_sync                    = 14<<6,
  58.     kMMCR0_PMC1_number_of_mtvscr            = 15<<6,
  59.     kMMCR0_PMC1_number_of_mtvrsave            = 16<<6,
  60.     kMMCR0_PMC1_vector_saturate_set            = 17<<6,
  61.     kMMCR0_PMC1_clean_L1_castouts_to_l2        = 18<<6,
  62.     kMMCR0_PMC1_I_Tablewalk_latency_over_TH    = 19<<6,
  63.     kMMCR0_PMC1_D_Tablewalk_latency_over_TH    = 20<<6,
  64.     kMMCR0_PMC1_stores                        = 21<<6,
  65.     kMMCR0_PMC1_dL1_load_hit                = 22<<6,
  66.     kMMCR0_PMC1_dL1_store_hit                = 23<<6,
  67.     kMMCR0_PMC1_dL1_total_hit                = 24<<6,
  68.     kMMCR0_PMC1_L2_tag_lookups                = 25<<6,
  69.     kMMCR0_PMC1_L2_tag_total_cycle_used        = 26<<6,
  70.     kMMCR0_PMC1_BIU_non_ARTRYd_data_TS_s    = 27<<6,
  71.     kMMCR0_PMC1_BIU_read_cycle_8_byte        = 28<<6,
  72.     kMMCR0_PMC1_Load_fold_queue_entries        = 29<<6,
  73.     kMMCR0_PMC1_dL1_write_hit_on_shd        = 30<<6,
  74.     kMMCR0_PMC1_writethrough_stores            = 31<<6,
  75.     kMMCR0_PMC1_iL1_miss_fetches            = 32<<6,
  76.     kMMCR0_PMC1_L2_d_side_read_hits            = 33<<6,
  77.     kMMCR0_PMC1_L2_i_side_read_misses        = 34<<6,
  78.     kMMCR0_PMC1_L2_dL1_castout_hits            = 35<<6,
  79.     kMMCR0_PMC1_L2_allocations                = 36<<6,
  80.     kMMCR0_PMC1_speculative_stalled_biu        = 37<<6,
  81.     kMMCR0_PMC1_dst_instruction_dispatched    = 38<<6,
  82.     kMMCR0_PMC1_dst_stream_0_line_fetches    = 39<<6,
  83.     kMMCR0_PMC1_dst_refreshed                = 40<<6,
  84.     kMMCR0_PMC1_dst_suspended                = 41<<6,
  85.     kMMCR0_PMC1_Raw_Snoop_Request            = 42<<6,
  86.     kMMCR0_PMC1_WOP_push_address_tenures    = 43<<6,
  87.     kMMCR0_PMC1_L2CO_snoop_hits                = 44<<6,
  88.     kMMCR0_PMC1_HIT_style_intervention_data    = 45<<6,
  89.     kMMCR0_PMC1_LFQ_touch_entries            = 46<<6,
  90.     kMMCR0_PMC1_L1OPQ_snoop_hits            = 47<<6,
  91.     kMMCR0_PMC1_vector_loads                = 48<<6,
  92.     
  93.     kMMCR0_PMC2_nothing                     = 0,
  94.     kMMCR0_PMC2_processor_cycles            = 1,
  95.     kMMCR0_PMC2_instructions_completed        = 2,
  96.     kMMCR0_PMC2_time_base_bit_transitions    = 3,
  97.     kMMCR0_PMC2_instructions_dispatched        = 4,
  98.     kMMCR0_PMC2_fall_through_branches        = 5,
  99.     kMMCR0_PMC2_ITLB_misses                    = 6,
  100.     kMMCR0_PMC2_vector_simple_integer        = 7,
  101.     kMMCR0_PMC2_vcfx_wait                    = 8,
  102.     kMMCR0_PMC2_Privileged_User_toggles        = 9,
  103.     kMMCR0_PMC2_Reserved_loads                = 10,
  104.     kMMCR0_PMC2_loads                        = 11,
  105.     kMMCR0_PMC2_snoops_serviced                = 12,
  106.     kMMCR0_PMC2_Dirty_L1_castouts_to_L2        = 13,
  107.     kMMCR0_PMC2_System_Unit_Instructions    = 14,
  108.     kMMCR0_PMC2_dL1_load_miss                = 15,
  109.     kMMCR0_PMC2_dL1_store_miss                = 16,
  110.     kMMCR0_PMC2_dL1_total_miss                = 17,
  111.     kMMCR0_PMC2_L2_tag_Write_cycles            = 18,
  112.     kMMCR0_PMC2_L2SRam_read_cycles            = 19,
  113.     kMMCR0_PMC2_BIU_ARTRYd_TS_s                = 20,
  114.     kMMCR0_PMC2_BIU_read_cycle_16_byte        = 21,
  115.     kMMCR0_PMC2_dRLT_SMM_occurrences        = 22,
  116.     kMMCR0_PMC2_L2_write_hit_on_shd            = 23,
  117.     kMMCR0_PMC2_cache_inhibited_stores        = 24,
  118.     kMMCR0_PMC2_iL1_reloads                    = 25,
  119.     kMMCR0_PMC2_L2_d_side_read_misses        = 26,
  120.     kMMCR0_PMC2_L2_i_side_read_misses        = 27,
  121.     kMMCR0_PMC2_L2_dL1_castout_misses        = 28,
  122.     kMMCR0_PMC2_L2_sectors_castouts            = 29,
  123.     kMMCR0_PMC2_dst_line_fetch_misses        = 30,
  124.     kMMCR0_PMC2_dst_stream_1_line_fetches    = 31,
  125.     kMMCR0_PMC2_dst_total_line_fetches        = 32,
  126.     kMMCR0_PMC2_dst_cancelled                = 33,
  127.     kMMCR0_PMC2_vector_fp_traps                = 34,
  128.     kMMCR0_PMC2_dRLT_snoops                    = 35,
  129.     kMMCR0_PMC2_HIT_style_modified_data        = 36,
  130.     kMMCR0_PMC2_snoop_events                = 37,
  131.     kMMCR0_PMC2_correct_speculative_branch    = 38,
  132.     kMMCR0_PMC2_dst_resume_due_to_context    = 39,
  133.     kMMCR0_PMC2_TLBI_instructions            = 40,
  134.     kMMCR0_PMC2_Snooped_TLBI                = 41,
  135.     kMMCR0_PMC2_BIU_TA_cycles                = 42,
  136.  
  137.     kMMCR0_Threshold                        = 1<<16
  138.  
  139. };
  140.  
  141.  
  142. // Constants for MMCR1 register
  143. enum
  144. {
  145.     kMMCR1_PMC3_nothing                            =  0 << 27,
  146.     kMMCR1_PMC3_processor_cycles                =  1 << 27,
  147.     kMMCR1_PMC3_instructions_completed            =  2 << 27,
  148.     kMMCR1_PMC3_time_base_bit_transitions        =  3 << 27,
  149.     kMMCR1_PMC3_instructions_dispatched            =  4 << 27,
  150.     kMMCR1_PMC3_taken_branches                    =  5 << 27,
  151.     kMMCR1_PMC3_DTLB_misses                        =  6 << 27,
  152.     kMMCR1_PMC3_vector_complex_instructions        =  7 << 27,
  153.     kMMCR1_PMC3_vector_float_wait                =  8 << 27,
  154.     kMMCR1_PMC3_TLBSync_instructions            = 10 << 27,
  155.     kMMCR1_PMC3_float_instructions                = 11 << 27,
  156.     kMMCR1_PMC3_store_conditionals                = 12 << 27,
  157.     kMMCR1_PMC3_snoop_interventions_from_L2        = 13 << 27,
  158.     kMMCR1_PMC3_second_speculative_branch_right    = 14 << 27,
  159.     kMMCR1_PMC3_stall_on_lr_ctr_dependency        = 15 << 27,
  160.     kMMCR1_PMC3_dL1_touch_hit                    = 16 << 27,
  161.     kMMCR1_PMC3_dL1_cache_operation                = 17 << 27,
  162.     kMMCR1_PMC3_dL1_total_cycles                = 18 << 27,
  163.     kMMCR1_PMC3_L2Tag_snoop_lookup                = 19 << 27,
  164.     kMMCR1_PMC3_L2SRAM_write_cycles                = 20 << 27,
  165.     kMMCR1_PMC3_dRLT_SMM_to_32_byte                = 21 << 27,
  166.     kMMCR1_PMC3_dst_line_fetch_dRLT_hit            = 22 << 27,
  167.     kMMCR1_PMC3_dst_stream_2_fetch                = 23 << 27,
  168.     kMMCR1_PMC3_number_of_dss                    = 24 << 27,
  169.     kMMCR1_PMC3_Snoop_Busies                    = 26 << 27,
  170.     kMMCR1_PMC3_L2_snoop_hits                    = 27 << 27,
  171.     kMMCR1_PMC3_HIT_style_exclusive_data        = 28 << 27,
  172.     kMMCR1_PMC3_BIU_write_of_8_byte                = 29 << 27,
  173.     kMMCR1_PMC3_dL1_reloads                        = 30 << 27,
  174.  
  175.  
  176.     kMMCR1_PMC4_nothing                            =  0 << 22,
  177.     kMMCR1_PMC4_processor_cycles                =  1 << 22,
  178.     kMMCR1_PMC4_instructions_completed            =  2 << 22,
  179.     kMMCR1_PMC4_time_base_bit_transitions        =  3 << 22,
  180.     kMMCR1_PMC4_instructions_dispatched            =  4 << 22,
  181.     kMMCR1_PMC4_mispredicted_branches            =  5 << 22,
  182.     kMMCR1_PMC4_DTLB_tablewalk_cycles            =  6 << 22,
  183.     kMMCR1_PMC4_vector_float_instructions        =  7 << 22,
  184.     kMMCR1_PMC4_vector_permute_wait                =  8 << 22,
  185.     kMMCR1_PMC4_Successful_store_conditionals    = 10 << 22,
  186.     kMMCR1_PMC4_Sync                            = 11 << 22,
  187.     kMMCR1_PMC4_BIU_KILL_transactions            = 12 << 22,
  188.     kMMCR1_PMC4_Interger_instructions            = 13 << 22,
  189.     kMMCR1_PMC4_Fetch_stall_due_to_bad_branch    = 14 << 22,
  190.     kMMCR1_PMC4_dL1_touch_miss_cycles            = 15 << 22,
  191.     kMMCR1_PMC4_dL1_snoop_intervention_cycles    = 16 << 22,
  192.     kMMCR1_PMC4_L2Tag_snoop_write                = 17 << 22,
  193.     kMMCR1_PMC4_L2SRAM_total_cycles                = 18 << 22,
  194.     kMMCR1_PMC4_dL1_castouts                    = 19 << 22,
  195.     kMMCR1_PMC4_dst_line_fetch_lD1_hit            = 20 << 22,
  196.     kMMCR1_PMC4_dst_stream_3_fetch                = 21 << 22,
  197.     kMMCR1_PMC4_dssall                            = 22 << 22,
  198.     kMMCR1_PMC4_dL1_snoop_hits                    = 23 << 22,
  199.     kMMCR1_PMC4_Hit_stype_shared_data            = 24 << 22,
  200.     kMMCR1_PMC4_BIU_write_cycle_of_16_bytes        = 25 << 22,
  201.     kMMCR1_PMC4_Snoop_interventions_from_dL1    = 26 << 22,
  202.     kMMCR1_PMC4_successful_tablewalks_by_dstX    = 27 << 22
  203. };
  204.  
  205. // Constants for MMCR2 register
  206. enum
  207. {
  208.     kMMCR2_ThresholdX2  = 0<<31,
  209.     kMMCR2_ThresholdX32 = 1<<31,
  210.     
  211.     kMMCR2_Use_PMON_IN  = 1<<30,
  212.     kMMCR2_USe_SMI         = 1<<29
  213. };
  214.  
  215.  
  216. void G4GetPMC( long *PMC1, long *PMC2, long *PMC3, long *PMC4);
  217. void G4ClearPMC( void);
  218. void G4SetMMCR0( long    MMCR0, long MMCR1, long MMCR2);
  219.  
  220. #ifdef __cplusplus
  221. }
  222. #endif
  223.  
  224. #endif